This invention relates generally to electronic amplifiers and more particularly to CMOS fixed gain amplifiers.
Amplifiers are commonly used in electronic applications. One example of the use of an amplifier is in a disk storage system commonly used in personal computers known as hard disk drives, HDD. U.S. Pat. No. 5,831,888 entitled xe2x80x9cAutomatic Gain Control Circuitxe2x80x9d and assigned to Texas Instruments Incorporated, the assignee of the present invention, sets forth generally the description of disk storage. The HDD device generally includes a magnetic storage media, such as rotating disks or platters, a spindle motor, read/write heads, an actuator, a preamplifier, a read channel, a write channel, a servocontroller, a memory and control circuitry to control the operation of the HDD and to properly interface the HDD to a host or system bus. The following U.S. Patents describe various aspects of HDD devices:
Prior art FIG. 1 illustrates a partial HDD system. A disk/head assembly 12 stores data. A magnetoresistive, MR, head 14 works through magnetic media to read data from disk 12 or to write data to disk 12. A write occurs through an inductive element in the MR head to the magnetic media disk assembly 12 and a read occurs by sensing the magnetic shifts in the disk assembly 12 by using the resistive read element of the MR head 14. A preamplifier 16, typically of the single ended variety, connects to MR head 14 to provide an initial amplification stage. The output of the preamplifier 16 is an analog signal which flows to a read channel 18 for further processing.
The read channel 18 in prior art FIG. 1 takes the analog signal from preamplifier 16 and conditions it to provide a digital output signal that will be sent by an appropriate bus structure to other components of a computer system, such as, for example, the digital signal processor in either the modem or the graphics card. An automatic gain control circuit 18a is the first part of the read channel 18. It provides an output signal having a larger amplitude than the input from preamplifier 16. A low pass filter 18b receives the amplified read signal and removes undesirable noise, such as high frequency noise, and generates a filtered read signal that is input to a fixed gain amplifier 18c. The output signal of the low pass filter 18b is typically a fairly large voltage input of around a 0.4 volt peak to peak differential. From there, the signal flows into a fixed gain amplifier, FGA, 18c. The fixed gain amplifier 18c provides sufficient amplification to the output of the low pass filter 18b to allow sample space processor 18d and digital processor 18e to perform the analog to digital conversion of the read signal.
There are several requirements that govern the design of fixed gain amplifier 18c. Power supply voltages are continually decreasing and are typically below 2.9 volts, at present, in CMOS applications. Given the low power supply, a CMOS amplifier still needs to have a really wide linear range and be fast enough to support the data rate at which the channel operates. The frequency range of the HDD is up to around 300 megahertz, at present. The output signal of low pass filter 18b, being about 0.4 volt peak to peak differential, is a very high input to the FGA 18c. If FGA 18c were just a regular differential pair, it would have a linear range of only about 26 millivolts which is very tiny. Additionally, one thing the FGA 18c should not do is to ruin what was done in the AGC 18a and the LPF 18b. So the total harmonic distortion, THD, should be very low, yet both the gain and a high bandwidth must be preserved. Additionally, the FGA 18c should provide a reasonable amount of amplification (typically around 4 V/V) and be manufacturable. That is, when built on silicon, it must be easy to match and be flexible.
Prior art FIG. 2 illustrates a fixed gain amplifier typical of the type used for FGA 18c. FGA 18c has two main parts: an amplifier core 20; and a common mode feedback circuit 22. In the amplifier core 20, the resistor RE1 is typically referred to as emitter degeneration resistor. Input transistors M1 and M2 are CMOS source followers. They follow the input voltage appearing at inputs Vin and VinB. Resistors RL1 and RL2 are the load resistors. Transistors M5 and M6 are cascoded devices. Transistor M5 and current source I5 form a cascoded mirror that is a high swing cascoded mirror. [In integrated circuit structures, when one device is connected on top of another device, (current source I5 is actually a MOS transistor in a silicon implementation) the structure is referred to as a cascoded stage.] Output transistors M5 and M6 are cascoded transistors that actually shield the mirroring transistors I5 and I6 (shown as ideal sources) so that the voltages on node 5 and node 6 don""t vary too much.
The common mode feedback circuit 22 of prior art FIG. 2, as the name implies, provides a mechanism to control the common mode voltage. It helps keep the dc values of the output nodes Vout and VoutB at a desired value independent of the variations in the manufacturing process and the fluctuations in the operating conditions. The common mode needs to be controllable because the next stage, the sample space processor 18d, can operate correctly only for a very narrow range of input common mode voltages. A very simple amplifier compares the reference common mode to the actual extracted common mode at the output. The circuit thus compares the common mode voltage to the average voltage at Vout and VoutB to see what the dc value of the output is. If the value is larger than the common mode, it needs to be brought down. If the value is smaller than the common mode, it needs to be brought up. The circuit folds transistors M9 and M10 into amplifier 20 and injects current on nodes N5 and N6 in order to affect the total DC current going through the load resistors RL1 and RL2 and consequently set the correct output common mode.
In prior art FIG. 2, the degeneration resistor RE1 on the input stage of the amplifier allows for a larger input voltage with a larger input voltage swing. By adding the degeneration resistor, the linear range of the amplifier is improved. The differential current that goes through the input source followers M1 and M2 is defined by the size of the resistor RE1 and the swing of the differential input voltage. With appropriate sizing of resistor RE1 the differential current going through M1 and M2 can be made reasonably smaller than the DC current going through M1 and M2, hence improving the linear range and reducing the overall distortion of the output signal. However, what brings in the majority of distortion to the amplifier is that the total currents through M1 and M2 are not independent of the input signal. In other words, the voltage gain across M1 and M2 instead of being constant is directly modulated by the variation in the input signal causing distortions in the output signal. The prior art circuit thus has gain dependant on the amplitude of the differential input signal making it unsuitable for very low distortion applications.
U.S. Pat. No. 5,142,242 to Schaffer, issued Aug. 25, 1992, provides a method of making the gain of the input transistors less dependant on the variation in the input signal. In the CMOS embodiment disclosed in FIG. 9, it provides a way to reduce the variation in the gain of the input transistors by mirroring the current at transistors Q8 to transistors Q10 and Q11. A problem with this approach, however is the mirror in the amplifier""s signal path creates a low frequency pole making the amplifier too slow for HDD applications where the usable frequencies extend into the 300 megahertz range. Another problem with this approach is that it is based on an inaccurate approximation that NMOS and PMOS transistors (Q6 and Q7 consequently) have identical behavior, needed for a complete cancellation of the distortion inherent to the recommended circuit topology. U.S. Pat. No. 5,451,901 to Welland, issued Sep. 19, 1995 uses a similar concept as the above ""242 patent to reduce the gain dependency on the variation in the input signal. MOS transistors M9 and M11 form a mirror that is similar to ""242 patent. It is a different way of forming a mirror, but it is still a current mirror. While this circuit is faster than the ""242 circuit, it is too slow for typical HDD applications. Node 78 and node 80 charge faster because of transistors M11 and M12 respectively, but they still form mirrors that are too slow. Moreover, the gain of input transistors M7 and M8 is not independent from the variation in the input signal, making the distortion level too high for common HDD applications.
What is needed, therefore, is a CMOS amplifier whose gain is very constant over a large dynamic range and is fast enough for HDD applications. It is accordingly an object of the invention herein to provide such an amplifier.
Other objects and advantages of the invention herein will be apparent to those of ordinary skill in the art having the benefit of the description herein.
A CMOS fixed gain amplifier incorporates super follower transistors into its input stage and folds the super follower transistors into its output stage to provide a constant gain over a large dynamic range for particular usefulness in hard disk drive applications.